DDR3

DDR3 is a kind of computer memory specification. It belongs to the family of memory products SDRAM, provides compared with DDR2 SDRAM higher operation efficiency and lower voltage, is four times DDR2 SDRAM (synchronous dynamic data rate of random access memory) increased to eight times continuator (currently popular), but the memory products.

Technology introduction

DDR3 SDRAM in order to save electricity, faster, use the transmission efficiency SSTL 15 I/O interface, operation I/O voltage is 1.5 V, adopt CSP, FBGA encapsulation packing, besides continuance of DDR2 SDRAM ODT, OCD, CAS, "AL control mode, another new outside the CWD, more diligence into ZQ, SRT, Reset, RASR function.

CWD is delayed, as written by Reset offers super province electricity function of DDR3 SDRAM, can let orders to stop operating, memory particles circuit into super province electricity standby mode, is a new ZQ resistor Calibration function, add the line provides ODCE (feet a Calibration On Die ODT (search) used to calibrate Die Termination) internal disruption On the resistance, and get Reflash Temperature (SRT) can BianChengHua Temperature control pulse function, SRT memory join let memory particles in Temperature, pulse and power management On when optimized, say, within the memory of the power management is done while allowing memory function, granular stability has been greatly ascend, ensure memory particles when high not work pulse, and burned the situation led to DDR3 SDRAM adds extra transportation charges RASR (get Array Refresh the function of local somebody Refresh, can say to somebody in the memory of doing more reading and writing in order to achieve effective information saves the electricity efficacy.

One, on the basis of DDR2 DDR3 in the new design.

1.8 bit prefetching design, and for 4bit prefetching DDR2, so that the frequency of DRAM kernel only equivalent data frequency 1/8, DDR [1] 3-800 core work frequency (100MHz kernel frequency) only.

2.adopt point-to-point topology structure, in order to reduce address/command and control bus burden.

3. Using 100nm below production craft, will work voltage from 1.8 V drop to 1.5 V, increase the asynchronous Reset (ZQ calibration Reset) and function.

Second, DDR3 and DDR2 several major difference:

1 sudden Burst Length, Length (BL)

Because the prefetching DDR3 for 8bit, so sudden Burst Length, transmission cycle (BL) also fixed for 8, and for DDR2 and early DDR structure system, the BL = 4 also is commonly used, 4bit DDR3 therefore added a Burst Chop (sudden mutation) mode, namely BL = 4 by a plus a read operation of BL = 4 write operation for synthesis of a sudden BL = 8, when the data transmission by A12 address line to control this sudden mode. And it should be pointed out that, any sudden interruption DDR3 memory in operation in, and did not support shall be prohibited, instead of the more flexible sudden transmission control (such as 4bit sequence sudden).

2. Addressing Timing (Timing)

Like DDR2 changes from DDR after delay, like the number DDR3 cycle than the CL cycle will also improve DDR2. The CL DDR2 in commonly 2 ~ 5 scope, and DDR3 is in between, between 5 ~ 11 and additional delay (AL) design also is changing. When the DDR2 AL range is 0 ~ 4, but when there are three kinds of DDR3 AL options, respectively is 0, CL - 1 and CL - 2. In addition, DDR3 also new added a timing parameters, delays (CWD), write the parameters according to specific working frequency will be determined.

3. New Reset (DDR3 Reset) function

Reset is an important new DDR3 function, and specially prepared a pin. DRAM industry long ago for increased this functionality, now finally achieved in DDR3. This pin will make DDR3 initialization processing become simple. When Reset DDR3 memory command efficient, and would stop all operation, switching to a minimum activity to save electricity. State

DDR3 memory during the Reset the inner will shut down most functions, all data receiving and transmitter will be closed, all internal procedures device will Reset, the DLL (delay phase-locked loop) and clock circuit will stop working, and ignore any movement of the data bus. Thus, will make the most DDR3 reach the purpose of saving power.

4. New DDR3 ZQ calibration function

ZQ is also a new feet, in this pin connected to a 240 ohm low tolerance reference resistance. This pin through a command set, through the chip Calibration Engine (On - Die Calibration started ODCE) to auto Calibration, data output driver of conduction resistance and ODT end resistance value. When the system is issued orders, will use the corresponding clock cycle (in plus electric and initialized with 512 clock cycle after the exit from the refresh operation, with 256 clock cycle, in other cases with 64 clock cycle) conduction resistance and ODT resistance to calibration.

5. Reference voltage is divided into two

In DDR3 system, for the memory system work very important reference voltage signal VREF will be divided into two signal that address signals for command and VREFCA and for data service, this VREFDQ of service bus will effectively improve the data in the system bus signal-to-noise level.

6. The point-to-point connections to the Point - the Point (P2P), -

This is to improve system performance and the important changes to the DDR3 and DDR2, is also a key distinction. In DDR3 system, a memory controller deal only with a memory channels, and the memory channels only one slot, therefore, the memory controller and DDR3 memory module between is peer-to-peer (P2P) relationship (single physical somebody module), or Point to double Point (the Point - to - to the Point, P22P) - somebody's relationship (double physics, thus greatly module) eased the address/orders/control and data bus load. And in memory module, and DDR2 category is similar, also have standard DIMM (PCS), DIMM/Micro - SO - DIMM (laptop), FB - DIMM2 (server) points, including the second generation FB - DIMM will use the specifications higher AMB2 (advanced memory buffer).

Facing the 64-bit architecture of the DDR3 obviously in frequency and speed has more advantages in DDR3, in addition, because the temperature automatic since refresh, according to local since other some functions, set in power loss DDR3 also do very well, therefore, it may first welcomed by mobile devices, like the first DDR2 memory is not meet as desktop but server. In the most rapid ascension CPU frequency, the PC desktop field DDR3 future is bright. Currently Intel promotes new chip - XiongHu Bear Lake), its (DDR3 specifications, and will support at the same time AMD is expected to support on the platform of DDR2 and K9 DDR3 two specifications.