QuickPath Interconnect

The technical characteristics of QPI

Greater bandwidth

Intel QuickPath Interconnect technology abbreviated as QPI, in fact it's official name is the CSI, Common System Interface, used to achieve between the chip interconnect directly, rather than through the FSB connection to Beiqiao, directed at the AMD HT bus. No matter the speed, bandwidth, each pin bandwidth, power and all other specifications to outdo HT bus.

QPI is based on a packet transmission serial type high speed point-to-point connection protocol, using differential signal with a special clock transmit. During the delay, QPI and FSB are almost identical, but can promote greater access to bandwidth. A group of QPI has 20 data transmission line, and transmitting ( TX ) and a receiver ( RX ) clock signal.

A QPI packet contains 80, takes two clock cycles or four transmission to complete the data packet transmission ( QPI clock signal rate transmission rate is half). At the end of each transmission of 20bit data, 16bit is true and valid data, the remaining four bits are used for the cyclic redundancy check, in order to improve the reliability of the system. Because QPI is bidirectional, sending can also receive the other end of transmitted data, so, each QPI bus bandwidth = every second transmission times (QPI frequency ) x each transmission of effective data (16bit / 8 = 2Byte ) x two-way. So QPI frequencies for 4.8GT / s of the total bandwidth = 4.8GT / s x 2Byte x 2 = 19.2GB / s, QPI frequencies for 6.4GT / s total bandwidth = 6.4GT / s x 2Byte x 2 = 25.6GB / s. ( bit -, Byte - byte, 1Byte = 8bit )

High efficiency

In addition, QPI another bright spot is the support of a number of system bus connection, called the Intel multi-FSB. System bus will be divided into a plurality of connection, and the frequency is not fixed, but also not as before and after FSB to connect. According to the system each subsystem of data throughput requirements, each system bus connection speed also can be different, the characteristics of no doubt than AMD current Hypertransport bus more elastic.